25 October 2017
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I designed an XOR gate using a static CMOS NAND gate design, allowing for a compact implementation. Three layers were used, poly, metal1, and metal2. The logic for the gate is shown below.

With a PMOS pull-up and NMOS pull-down, results are strong for both 0 and 1 outputs. You can download the extracted layout above which works with Virtuoso by Cadence.